1. Field of the Invention
The present invention relates to voltage scaling and, more particularly, to a power supply system and method that provides a low-cost approach to voltage scaling.
2. Description of the Related Art
A DC power supply system is a circuit that provides a supply voltage and current to a load. Significant power savings can be obtained by changing the supply voltage in response to changes in the clock signal. This process, known as voltage scaling, corresponds with changes in the operational mode of the load.
For example, when a processor is performing intensive computations at the maximum clock speed, the supply voltage applied to the logic within the processor is sufficient to meet the timing requirements of the processor. When there are no further computations to be performed, the operational mode of the processor can be changed so that the processor is placed into a sleep mode where the frequency of the clock signal is dramatically lowered.
When the frequency of the clock signal is lowered, the period of the clock signal is increased. As a result, the magnitude of the supply voltage that is applied to the logic within the processor can be significantly lowered and still meet the timing requirements of the processor.
FIG. 11 shows a circuit diagram that illustrates a prior art DC power supply system 1100 that changes the supply voltage in response to changes in the clock signal. As shown in FIG. 11, power supply system 1100 includes a clock generator 1110 that outputs an input clock signal ICLK and a sample clock signal SCLK. In addition, the sample clock signal SCLK is a quadrature signal with respect to the input clock signal ICLK (is delayed 90° with respect to the input clock signal ICLK).
Power supply system 1100 also includes a propagation delay detector 1112 that detects the propagation delay of the input clock signal ICLK as clocked by the sample clock signal SCLK, and outputs a multi-bit propagation delay word PDW that identifies the measured propagation delay.
For example, propagation delay detector 1112 can include a number of substantially-equal, serially-connected delay blocks that have a corresponding series of outputs. The series of outputs form the inputs to a series of latches which are clocked by the sample clock signal SCLK.
In operation, the rising edge of the input clock signal ICLK is input to the first delay block of the series. The input clock signal ICLK propagates through each succeeding delay block in the series until the rising edge of the sample clock signal SCLK clocks each of the latches, thereby capturing the logic states at the outputs of the delay blocks.
Referring again to FIG. 11, power supply system 1100 also includes a changing clock frequency detector 1114 that receives the propagation delay word PDW from propagation detector 1112. In response, detector 1114 generates a binary word BW that represents changes in the propagation delay word PDW which, in turn, represent changes in the frequency of the input clock signal ICLK.
In addition, power supply system 1100 includes a pulse width modulator 1116 that outputs a pulse width modulated signal PWM where the widths of the pulses are defined by the values of the binary words BW that are output from changing clock frequency detector 1114.
Power supply system 1100 further includes a level shifter and high voltage driver 1120 that level shifts and outputs a voltage in response to the pulse modulated signal PWM. Driver 1120 includes a PMOS driver transistor 1122 that has a source connected to a voltage VDD, a drain connected to an inductor node NL, and a gate.
Driver 1120 also has an NMOS driver transistor 1124 that has a source connected to ground, a drain connected to inductor node NL, and a gate. Driver 1120 additionally includes a gate signal generator 1126 that receives the pulse width modulated signal PWM, and outputs non-overlapping gate signals G1 and G2 to PMOS transistor 1122 and NMOS transistor 1124, respectively.
In operation, when the pulse width modulated signal PWM transitions low, generator 1126 turns off NMOS transistor 1124 via gate signal G2, and then turns on PMOS transistor 1122 via gate signal G1. When PMOS transistor 1122 turns on, transistor 1122 sources current into inductor node NL.
When the pulse width modulated signal PWM transitions high, generator 1126 turns off PMOS transistor 1122 via gate signal G1, and then turns on NMOS transistor 1124 via gate signal G2. When NMOS transistor 1124 turns on, transistor 1124 provides a continuous conductive path to ground for inductor node NL.
As further shown in FIG. 11, power supply system 1100 also includes a filter 1130 that generates a DC voltage on a power node PN. Filter 1130 includes an inductor L that is connected to transistors 1122 and 1124 and the power node PN, and a capacitor C that is connected to the power node PN and ground.
The power node PN is connected, and provides a supply voltage, to a DC load, such as a microprocessor or memory. In addition, the power node PN is connected to the elements of power system 1100, with the exception of level shifter and high voltage driver 1120 (FIG. 11 only shows the power node PN connected to propagation delay detector 1112 for clarity).
Thus, power supply system 1100 provides a supply voltage and current to a power node that varies as the frequency of the clock signal varies. As noted above, by varying the supply voltage in response to variations in the clock signal, significant power savings can be realized.
One drawback of power supply system 1100 is that transistors 1122 and 1124 of level shifter and driver 1120 introduce noise into the supply voltage that results from transistors 1122 and 1124 switching off and on. This noise cannot be easily eliminated (spread spectrum techniques can mask the noise), and is intolerable in many radio applications such as cell phones.
Another drawback of power supply system 1100 is that system 1100 utilizes large, relatively-expensive, external components, such as a 10 uF capacitor and an even more costly 10 uH inductor, to implement filter 1130. In addition to a large size, inductors are another source of noise.
Filter 1130 can also be implemented with two capacitors (and without inductors). This approach, however, is less efficient, and only moderately less expensive than an LC filter. In addition, linear regulators, such as low-drop out regulators, can also be used, but are significantly more expensive.
Thus, there is a need for a low-cost approach to reducing the noise generated by the switching transistors, and providing a supply voltage and current to a power node that varies as the frequency of the clock signal varies.